A successful and widely deployed Instruction Set Architecture (ISA) in the world is the Arm instruction set. To date, over 300 billion Arm ISA-based processors have been deployed.[1] With a global population of over eight billion,[2] that is approximately 38 Arm cortex processors per person.
What makes the Arm ISA so attractive is that it is part of the reduced instruction set computer (RISC) architectures and is designed to be used across a range of applications, from small battery-powered applications to real-time control and high-performance at the edge and cloud. To support these use cases, the Arm architecture has evolved over the years from Armv1 to the current Armv9-A.
The Arm cortex range comprises three different groups of processors that can be selected to implement solutions for their applications.
- Cortex-M: This microcontroller class of processors is intended for low-level implementations closer to the hardware. They are designed to be low cost and low power. Typical applications might include controlling sensors and managing system IO, displays, and battery chargers. Normally, Cortex-M processors do not run operating systems like Linux because a memory management unit is not provided.
- Cortex-R: This processor is intended for use in real-time and safety-critical applications. To support real-time functions, they include tightly coupled memories, the ability to run in lockstep, memory protection units, and error correcting codes on caches and tightly coupled memory (TCM). Cortex-R processors also provide deterministic interrupts, key for real-time applications. Typically, Cortex-R class processors run a real-time operating system.
- Cortex-A: This application-class processor is intended for implementation of high-performance software applications that require full operating systems or hypervisors. Cortex-A class processors also include elements such as NEON to provide single instruction multiple data (SIMD), vector floating point (VFP) units, and TrustZone, which provides orthogonal worlds for security.
Cortex-M uses a 32-bit ISA, while Cortex-R and Cortex-A provide both 32- and 64-bit architectures.
One of the key distinguishing factors of the Arm architecture is the Thumb-2 instruction set. The original Thumb instruction set was a 16-bit encoding of the Arm ISA. Thumb-2 extended the original instruction set to provide support for 32-bit instructions, creating a variable length instruction set. Thumb-2 achieves similar code density but increases performance at the same time. Processors within the Cortex-A and Cortex-R ranges can operate either standard Arm ISA or Thumb-2, while several processors within the Cortex-M range operate only with the Thumb-2 instruction set, since memory is typically more limited.
Of course, the processor itself is not the only element needed by designers. Arm has also developed interconnect specification such as the Advanced Microcontroller Bus Architecture (AMBA), which defines several interface standards that can be used with its processor cores to create multi-processing solutions and add a range of peripherals. AMBA includes simple interfaces to transfer memory-mapped data, such as AXI Lite and more complex interfaces that support high-bandwidth transactions like AXI, along with cache coherent interconnects (CCIs) to enable cache coherency across a multi-processor system.
It is these interfaces that processor vendors licensing Arm cores use to create their processor offerings. These interfaces enable developers to customize the offering for different applications—one of the most popular Arm Cortex-based processor families are the STM32. These offer a range of Arm-based processors that include an array of on-chip peripherals, such as UARTs, SPI, and I2C, to more complex peripherals like USB, camera interfaces, CAN, and Ethernet. These choices allow developers to select the most appropriate core to address the application requirements.
Most Arm cores are deployed at the edge. Some applications are deployed in the cloud, such as vision guided robotics (Cortex-A class), autonomous vehicle operation (Cortex-R Class), or monitoring industrial control.
Increasingly, edge applications are seeing deployments of machine learning (ML) inference. This can be in Cortex-A class processors for image recognition, where the power of an application-class processor is required. Alternative ML deployments may use Cortex-M class processors to implement predictive maintenance systems. One example of predictive maintenance would be in the monitoring of current drawn on power rails, where using an ML inference model can determine if the system was on a path to failure. This type of application is one of the more critical use cases of ML at the edge. Typically, health and monitoring systems are implemented using Cortex-M class processors. This class of processors is not suitable for the implementation of full ML stack applications. However, TinyML frameworks are increasingly popular for solutions in processors with the capabilities of the Cortex-M class processors. TinyML frameworks support 32-bit architecture, so they enable Cortex-M class processors to implement machine learning frameworks that previously required higher classes of performance.
Conclusion
No matter what application you are developing, from image processing and machine learning to robotics, industrial control, health monitoring, and more, there is an Arm Cortex device that can be used to implement it. This applicability stems from the Arm ISA’s compact code footprint and support for a range of industry standard interfaces and frameworks, along with a wide developer base familiar with deploying Arm Cortex targets.
Sources
[1]https://www.arm.com/architecture/cpu#:~:text=It%20is%20the%20most%20pervasive,Integrated%20security
[2]https://www.census.gov/newsroom/press-releases/2024/population-new-years-day.html.
