MathWorks has announced the availability of EDA Simulator Link 3.3 with new FPGA-in-the-loop (FIL) capabilities for Xilinx FPGA development boards.
According to MathWorks, FIL enables engineers to verify their designs at hardware speeds while using Simulink as a system-level test bench.
The introduction of FIL adds to the set of HDL verification options that EDA Simulator Link supports for algorithms created in MATLAB and Simulink.
FPGA-based verification reportedly provides significantly higher run-time performance than is possible with HDL simulators and increases confidence that the algorithm will work in the real world.
The company says key product features include the ability to verify HDL implementations of MATLAB code and Simulink models using FPGA development boards for both Spartan and Virtex class devices including the Virtex-6 ML605 development board as well as
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